The present invention relates to a thin film transistor, and more particularly to a lightly doped drain (LDD) structure of the thin film transistor. The present invention also relates to a process for producing such an LDD structure of a thin film transistor.
With the increasing development of integrated circuits, electronic devices have a tendency toward miniaturization. As is known, TFTs (Thin Film Transistors) are widely used as basic elements for controlling pixels of a TFT liquid crystal display (TFT-LCD). As a result of miniaturization, a channel between a source region and a drain region in each TFT unit will become narrower and narrower. Therefore, a short channel effect is likely to occur. Such short channel effect possibly causes the TFT unit to be undesirably turned on even when the gate voltage is zero. The switch function of the transistor is thus failed. In addition, the electric field intensity at the channel increases due to the short distance. Therefore, hot electrons in the vicinity of the drain region have a higher energy compared with the energy gap of the semiconductor. The electrons in valence bands might be promoted to conduction bands when being collided by the hot electrons, thereby producing many electron-hole pairs. Such phenomenon is also referred as a xe2x80x9chot electron effectxe2x80x9d.
In a TFT-LCD, the TFT units are typically formed on a glass substrate. Since the glass substrate is generally not heat resistant, the process for producing TFTs on the LCD glass plate should be a low-temperature manufacturing process. In order to minimize the hot electron effect, a low-temperature polysilicon thin film transistor (LTPS-TFT) having LDD (lightly doped drain) structures was developed. In these LTPS-TFTs, a gate-drain overlapped LDD (GO-LD) structure was widely employed.
A process for producing such an N-type LTPS-TFT is illustrated with reference to FIGS. 1(a) to 1(g). In FIG. 1(a), a silicon-oxide buffer layer 11 and an intrinsic amorphous silicon (i-a-Si) layer are sequentially formed on a glass substrate 10. Then, the i-a-Si layer is converted to an intrinsic polysilcon (i-poly-Si) layer 12 by a laser annealing procedure. Then, by a micro-photolithography and etching procedure, the i-poly-Si layer 12 is partially etched to form a desired polysilicon structure 120, as can be seen in FIG. 1(b). In FIG. 1(c), a photoresist layer is formed on the polysilicon structure 120 and properly patterned to be a mask 13. Then, two N-type regions 121 and 122 are formed on a portion of the polysilicon structure 12 exposed from the mask 13 by an ion implantation procedure. The two N-type regions 121 and 122 serve as source/drain regions of an N-channel TFT. After the photoresist mask 13 is removed, a gate insulator 14, for example made of silicon dioxide, is formed on the resulting structure of FIG. 1(c), as shown in FIG. 1(d). In FIG. 1(e), a gate electrode 15 is then formed on the gate insulator 14 by sputtering and patterning a gate conductive layer on the resulting structure of FIG. 1(d). Then, by a lightly ion implantation procedure with the gate electrode 15 serving as a mask to provide trace N-type dopants into the polysilicon structure 120, two LDD (lightly doped drain) regions 123 and 124 are formed immediately adjacent to the drain/source regions 121 and 122, respectively. In FIG. 1(f), an interlayer dielectric layer 17 is formed on the resulting structure of FIG. 1(e). Then, a proper number of contact holes directing to the gate electrode and source/drain regions are created. Afterwards, as shown in FIG. 1(g), a conductive layer is sputtered on the resulting structure of FIG. 1(f), fills the contact holes, and then patterned to form a gate conductive line 190 and a source/drain conductive line 191.
The gate-drain overlapped LDD (GO-LD) structure results in a reduced electric field intensity in the vicinity of the drain region so as to slightly diminish the influence of the hot electron effect. However, with the increasing demand of high resolution of the display, the circuitry is more and more complicated than ever. In other words, the number of the electronic devices increases significantly so as to reduce the space of a single electronic device. Accordingly, the channels of transistors will become narrower and narrower. Furthermore, the LDD regions shorten the channel to an extent, and thus depletion regions in the vicinity of the source/drain regions will be relative close and even reachable to each other. Therefore, current leakage and punch-through problems may occur so as to deteriorate the electronic devices. The above-described effects will be even significant with the increasing development toward miniaturization.
It is an object of the present invention to provide a thin film transistor having diminished hot electron, current leakage and punch-through effects.
It is another object of the present invention to provide a process for producing a thin film transistor having a particular LDD structure to reduce hot electron, current leakage and punch-through effects.
In accordance an aspect of the present invention, there is provided a thin film transistor. The thin film transistor comprises a semiconductor layer, source/drain structures, a single LDD structure, a gate structure and an insulator layer. The semiconductor layer is formed of a semiconductor material such as polycrystalline silicon, and the semiconductor layer is disposed on a glass substrate. The source/drain structures are formed apart from each other in the semiconductor layer. The single LDD structure is disposed between the source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side spaced from a second one of the source/drain structures by essentially the semiconductor material. The gate structure is formed over the semiconductor layer. The insulator layer is disposed between the semiconductor layer and the gate electrode for insulating the gate electrode from the source/drain structures and the LDD structure.
In an embodiment, the single LDD structure is a gate-drain overlapped LDD. The first one of the source/drain structures is the drain structure, and the second one of the source/drain structures is the source structure.
In an embodiment, the thin film transistor is of an N-type, and the LDD structure contains a doping material selected from a group consisting of P ions, As ions, PHx ions, AsHx ions and a combination thereof.
In accordance with another aspect of the present invention, there is provided a thin film transistor. The thin film transistor comprises a semiconductor layer, source/drain structures, a first LDD structure, a second LDD structure, a gate structure and an insulator layer. The semiconductor layer is formed of a semiconductor material. The source/drain structures is formed apart from each other in the semiconductor layer. The first LDD structure is disposed between the source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side opposed to the first side. The second LDD structure having a third side adjacent to the second side of the first LDD structure, and a fourth side spaced from a second one of the source/drain structures by essentially the semiconductor material. The gate structure formed over the semiconductor layer. The insulator layer is disposed between the semiconductor layer and the gate electrode for insulating the gate electrode from the source/drain structures and the LDD structures.
In an embodiment, each of the first and second LDD structures is a gate-drain overlapped LDD. The thin film transistor is of an N-type, the first LDD structure contains a doping material selected from a group consisting of P ions, As ions, PHx ions, AsHx ions and a combination thereof, and the second LDD structure contains more than one doping material selected from a group consisting of B ions, BHx ion, B2Hx ions and a combination thereof.
In an embodiment, the thin film transistor further comprises a third LDD structure and a fourth LDD structure. The third LDD structure is disposed between the source/drain structures, and having a fifth side adjacent to the second one of the source/drain structures and a sixth side opposed to the fifth side. The fourth LDD structure has a seventh side adjacent to the sixth side of the third LDD structure, and an eighth side spaced from the fourth side of the second LDD structure by essentially the semiconductor material. The third LDD structure contains a doping material selected from a group consisting of P ions, As ions, PHx ions, AsHx ions and a combination thereof, and the fourth LDD structure contains more than one doping material selected from a group consisting of B ions, BHx ion, B2Hx ions and a combination thereof.
In an embodiment, at least a portion of the first and third LDD structures is exposed from the second and fourth LDD structures and the source/drain structures.
In an embodiment, the first LDD structure is enclosed with the second LDD structure and the first one of the source/drain structures, and the second LDD structure is enclosed with the fourth LDD structure and the second one of the source/drain structures.
In according to another aspect of the present invention, there is provided a process for forming a thin film transistor. A gate insulator layer is formed on a semiconductor layer. Then, a gate structure is formed on the gate insulator layer. Then, source/drain structures are formed in the semiconductor layer, wherein the source/drain structures are spaced from each other by a channel region. Then, a first kind of doping material is injected into a first end portion of the channel region in a first direction of a first angle from a surface of the semiconductor layer to form a first LDD structure, and a second kind of doping material is injected into the first end portion of the channel region in a second direction of a second angle from the surface of the semiconductor layer to form a second LDD structure in contact with the first LDD structure.
In an embodiment, the first kind of doping material is selected from a group consisting of P ions, As ions, PHx ions, AsHx ions and a combination thereof, and the second kind of doping material contains at least one member selected from a group consisting of B ions, BHx ion, B2Hx ions and a combination thereof.
In an embodiment, the step of injecting the first kind of doping material is performed over the channel region with the gate structure serving as a mask, and a third LDD structure is simultaneously formed in a second end portion of the channel region opposite to the first end portion when the first LDD is formed.
In an embodiment, the process for forming a thin film transistor further comprises a step injecting a third kind of doping material into the second end portion of the channel region in a third direction of a third angle from the surface of the semiconductor layer to form a fourth LDD structure in contact with the second LDD structure.
Preferably, the first angle is substantially 90xc2x0, and each of the second angle and the third angle is greater than 0xc2x0 and no greater than 30xc2x0.
Preferably, the third kind of doping material is the same as the third kind of doping material.
In an embodiment, the gate structure includes a gate electrode and a spacer structure beside the gate electrode, and the step of injecting the first doping material is performed after the spacer structure is removed.